AR# 15894: LogiCORE RapidIO - Why is LNK_TDST_RDY_N asserted before the PHY has trained?
LogiCORE RapidIO - Why is LNK_TDST_RDY_N asserted before the PHY has trained?
Why is LNK_TDST_RDY_N asserted before the PHYS has trained? Shouldn't the buffer be prohibited from sending data when LNK_TRDY_N is not asserted?
When the PHY comes out of reset, it can accept data from the buffer even though it has not trained. This is because the PHY contains FIFOs that can be loaded with data. If data is placed into the buffer, the buffer will begin to send data to the PHY and LNK_TDST_RDY_N will go High after the FIFO starts filling up. Once the PHY has trained, it will send the data over the link and re-assert LNK_TDST_RDY_N to the buffer so that more data can be transferred to the PHY.