This will execute the installer and install the service pack into your %XILINX_EDK% area. Follow the instructions in the installer to complete the installation. A successful installation of the EDK will update your software version number to Xilinx EDK 3.1.2 Build EDK_C.17.
(Xilinx Answer 16215) 3.1 EDK - Platform Generator can rerun XST when the HDL code in the "myip" directory changes. (Xilinx Answer 16216) 3.1 EDK - Platform Generator generates an incorrect VHDL file for an OPB ATMC core. (Xilinx Answer 16067) 3.1 EDK - The DCR_DBus of OPB2PLB_BRIDGE is connected to GND when a DCR interface is enabled.
(Xilinx Answer 16209) 3.1 Library Generator - The memory map associated with each processor is now printed out.
A successful installation of EDK Service Pack 1 will update your software version number to 3.1.1.
NOTE 1: The destination directory specified during the set-up operation must contain an existing EDK 3.1 installation. Only existing files will be updated.
NOTE 2: The EDK 3.1 environment variables should be set before commencing the installation of Service Pack 1.
This will execute the installer and install the service pack into your %XILINX_EDK% area. Follow the instructions in the installer to complete the installation. A successful installation of the EDK will update your software version number to Xilinx EDK 3.1.1 Build EDK_C.13.
- The new "Add/Edit Cores" dialog box does not check for invalid entries other than rudimentary ones.
- Compiler options cannot be set on individual source and header files in a project.
- When header files are added to a project, the header file path is not automatically taken as an include path. You must specify include paths in the "Compiler Options" dialog box.
- All XPS commands should be given in the project directory (no window mode) .
2. Library Generator:
- LibGen cannot process integer MPD parameters that are specified with an underscore character ("_"). For example, "C_CLK_FREQ" in UART should not include an "_" when it is used in the MHS file and must be defined in "xparameters.h".
- PSFutil is not supported for Solaris.
1. The processor IP is written only in VHDL; hence, Verilog behavioral simulation cannot be performed.
2. Because certain cores have been changed and/or made obsolete, you must perform the following steps:
- Update ModelSim models for cores in EDK. - First, ensure that a modelsim.ini file exists in the current directory or that an environment variable called "MODELSIM" is pointing to an existing file. If this is not the case, copy it from the MODELSIM installation area. - Run the following:
3. For the latest MTI versions (5.5f or later), create a modelsim.ini file in the directory in which vmap_edk_libs is run. This may be copied from the MODELSIM installation directory.
If you do not do this, the modelsim.ini file in the MODELSIM installation directory will be modified.
(This issue will be fixed in the next Service Pack.)
ISSUES ADDRESSED IN EDK SERVICE PACK 1
- Support for Windows XP has been added.
- The PowerPC Linker of C.10.5.1 build generates an incorrect executable.
- An incorrect XPAR_XGPIO_NUM_INSTANCES parameter is specified in "xparameters.h". - LibGen does not report an error when an invalid driver level exists in the MSS. - LibGen fails to include the "opb2plb" device driver. - LibGen does not pull in bridges as part of a processor's addressable window. - "xparameters.h" should not have extern for Level 0 drivers when the intc level is 1.
- mb-gcc: Different results occur when different optimization levels are set. - gcc: Long types report incorrect answers in several math functions.
- User control over the manner in which INOUT ports are implemented in HDL is now permitted. - PlatGen reports an erroneous error message when a duplicate parameter exists. - The PlatGen cache does not work for the BRAM block. - JTAG VEC tie-offs for the PPC405 MPD have been updated.
- 3.1i EDK Revup utility: Revup is adding an unnecessary POSITION attribute.
- The system.do file created by SimGen does not create a work library. - The system.do file contains incorrect .vhd extensions for a Verilog behavioral simulation. - SimGen does not create a local copy of the modelsim.ini file under the simulation directory as it should. - A system cannot be loaded into MTI with system.do; "-L simprim_ver" is needed for Verilog.
- The "Bootstrap" mode has been removed. - XMD and XPS cannot locate a valid init.tcl file on Solaris machines.
- XPS does not support printing/displaying variables that are set by XSET. - A display showing "Analyzing MHS" has been added to XPS. - The system.log file is not "cleaned" when Run -> Clean -> All is run. - The "delete" key cannot be used to remove sources/headers. - The system.make target menu has been updated. - XPS reports erroneous error messages when re-synchronizing. - SimGen: refers to UniSim in the "bram_block" model. - XPS does not create all required directories when a new project is created. - "mb-size" has been added. - The "F3" hot key does not "Find Next" in the Edit menu. - XSET DEV does not work. - XPS does not always display device and other project options. - XPS rewrites MSS/MVS files even if they have not changed. - The number of buttons on the XPS toolbar has been reduced. - MTI cannot be started in XPS. - When XMP is loaded, the MSS file is overwritten. - When an XMP file is loaded on the XPS command line, the MSS file is overwritten. - Unusual/incorrect error messages are reported in XPS. - The Add Cores list is not created in the necessary order. - Components cannot be deleted from the MHS in the Source window.