The number of VHDL files System Generator creates for large designs can easily exceed one hundred. This can have negative side effects on the design flow, including slow speeds and the crashing of the Synthesis tools. Project Navigator can also be greatly slowed.
How do I reduce the number of files created?
A Perl script called "vhdljoin.pl" is available in the installation directory ($MATLAB/toolbox/xilinx/sysgen/scripts). This script can be used to merge all the individual VHDL files into a single VHDL file.
This can solve speed and crashing issues for certain synthesis tools, but it will not improve the speed of the Project Navigator environment in the Xilinx ISE software; in fact, it will slow the environment down. Hence, we recommend use of the script only if you are using third-party synthesis tools and experiencing severe run-time problems.