AR# 16039

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5.2i XST - How do I use the rom_style attribute for XST?

Description

Keywords: VHDL, Verilog, block, RAM, ROM, directive

Urgency: Standard

General Description:
The rom_style attribute does not appear to be working. How do I use this attribute in XST?

NOTE:
- For information on inferring block ROM, see (Xilinx Answer 15639).
- For information on known issues with inferring block ROM, see (Xilinx Answer 16026).

Solution

1

The attribute is placed on the signal that represents the combinatorial logic in your inferred ROM.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity top is
port (clk,en : in std_logic ;
addr : in std_logic_vector (7 downto 0);
dout : out std_logic_vector (3 downto 0));
end;

architecture rtl of top is

type rom is array (0 to 255) of std_logic_vector (3 downto 0);
constant ROM1 : rom := (
"0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111",
"1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111",

:
:
:
signal temp_data : std_logic_vector( 3 downto 0);

attribute rom_style : string;
attribute rom_style of temp_data : signal is "Distributed";

begin

temp_data <= rom1(conv_integer(addr));

process (clk)
begin
if (rising_edge (clk)) then
if (en = '1') then
dout <= temp_data;
end if;
end if;
end process;

end rtl ;

This problem is fixed in the latest 5.2i Service Pack, available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 5.2i Service Pack 1.

2

The attribute is placed on the signal that represents the combinatorial logic in your inferred ROM.

Verilog

module top (clk,en,addr,dout);

input clk,en;
input [3:0] addr;
output [4:0] dout;

reg [4:0] temp_data, dout;

always @ (posedge clk)
if (en) dout <= temp_data;

always @ (addr)
begin

case (addr)
4'b0000 : temp_data = 5'b00000;
4'b0001 : temp_data = 5'b00001;
4'b0010 : temp_data = 5'b00010;
4'b0011 : temp_data = 5'b00011;
4'b0100 : temp_data = 5'b00100;
4'b0101 : temp_data = 5'b00101;
4'b0110 : temp_data = 5'b00110;
4'b0111 : temp_data = 5'b00111;
4'b1000 : temp_data = 5'b01000;
4'b1001 : temp_data = 5'b01001;
4'b1010 : temp_data = 5'b01010;
4'b1011 : temp_data = 5'b01011;
4'b1100 : temp_data = 5'b01100;
4'b1101 : temp_data = 5'b01101;
4'b1110 : temp_data = 5'b01110;
4'b1111 : temp_data = 5'b01111;
endcase

end
// synthesis attribute rom_style of temp_data is "distributed"

endmodule
AR# 16039
Date 10/20/2005
Status Archive
Type General Article
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