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AR# 16107

5.1i ECS, Behavioral Simulation, VHDL - The output of an IOBUF is always "X"

Description

Keywords: ECS, behavioral, simulation, IOBUF, X, IO_DUMMY, incorrect

Urgency: Standard

General Description:
When I use the ECS schematic tool, the output of an IOBUF is always "X in the behavioral simulation.

This problem is caused by a bug that affects the way in which the VHDL for the schematic is created.

The following example shows a snippet of the VHDL that is generated:
BEGIN
IO <= IO_DUMMY;
XLXI_1 : IOBUF
PORT MAP (I=>my_out, IO=>IO_DUMMY, O=>my_in,
T=>T);
END SCHEMATIC;

Notice that a dummy signal was created; the top-level I/O port is set = to IO_DUMMY. This works when the IOBUF is used as an output buffer. The value comes out of the IOBUF, goes to IO_DUMMY, and then moves out to the I/O. But when the IOBUF is used as an input, there is no way for the value to be passed on to the IOBUF. The value comes in on the I/O, but IO_DUMMY is never set equal to the I/O, so the IOBUF cannot acquire the value.

Solution

1

To work around this problem, modify the VHDL that was created for the schematic. When the dummy signal is removed and I/O is connected directly to I/O, the output will be correct.

For example:
BEGIN
XLXI_1 : IOBUF
PORT MAP (I=>my_out, IO=>IO, O=>my_in, T=>T);
END SCHEMATIC;

2

Another way to work around the problem is to change the Synthesis flow to Verilog, as the Verilog HDL will be created correctly. (This solution also requires that the testbench be created in Verilog.)
AR# 16107
Date Created 11/11/2002
Last Updated 01/08/2006
Status Archive
Type General Article