AR# 16109

5.1i IP1 CORE Generator - Known Issues for CORE Generator in 5.1i IP Update #1 (also referred to as 5.1i IP1 or F_IP1)


Keywords: COREGen, Known, Issues, 5.1i

Urgency: Standard

General Description:
This Answer Record contains known issues addressed in 5.1i IP Update #1 (also referred to as 5.1i IP1 or F_IP1).



Software Compatibility

Acrobat Reader Requirement
Acrobat Reader Version 4 or later must be installed for core data sheets to be viewed. You can download the latest Acrobat software from the following Adobe site:

Windows 2000/XP
- If you use a Windows platform, Xilinx recommends that you use the "High Color" setting for your display.
Please see (Xilinx Answer 12372).

- The CORE Generator GUI is not displayed in the Windows task bar when I double-click the XCO file in an ISE project.
Please see (Xilinx Answer 11386).

- The CORE Generator GUI pages are out of sequence when I cycle through the options for a core.
Please see (Xilinx Answer 16191).

- Clicking on the Web Browser button does not open Netscape on Solaris and the following message is reported:
"Netscape: Couldn't find our resources?"
Please see (Xilinx Answer 11771).

- CORE Generator does not work with Netscape 4.72 when it is launched from Project Navigator on Solaris.
Please see (Xilinx Answer 14793).

Xilinx Implementation Software Issues
- When a design is imported from the 3.1i software, "port mismatch " and "unconnected ports" messages are reported during simulation and implementation.
Please see (Xilinx Answer 13062).

Updates Installer Tool
- The Updates Installer Tool has been disabled for the remainder of the 5.x release. A problem found late in the 5.2i release allowed the installation of IP updates that were incompatible with the installed Xilinx software version.

For information on the latest available CORE Generator IP Updates, refer to the Xilinx Software Updates and follow the instructions for downloading and installing these updates manually:

- The Updates Installer Tool cannot be used to install cores that have been captured by the IP Capture Tool.
Please see (Xilinx Answer 14183).

- The installer may take several hours, or the process seems to hang.
Please see (Xilinx Answer 12544).

IP Capture Tool
- When I use the IP Capture tool, the following error is reported:
"ERROR: Cannot open file <./XilinxCoreLib/vhdl_analyze_order> for writing. No analyze order list will be generated."
Please see (Xilinx Answer 14850).

Other Known Issues
- An "Update Project" box appears when I open a project with multiple repositories.
Please see (Xilinx Answer 12345).

- XST synthesis fails and the following error is reported:
"ERROR: SimGenerator: Failure of Sim to implement customization parameters core decode_810".
Please see (Xilinx Answer 14684).


DA FIR v7.0, DDC v1.0 GUI, and MAC FIR v1.0
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.
Please see (Xilinx Answer 14202).

LogiCORE DDS v4.1
- When the Xilinx Implementation tool is run with DDS v4.1, the following error is reported:
"ERROR:Place:1751 - Structured logic associated with an F7 configuration could not be placed."
Please see (Xilinx Answer 14122).

LogiCORE Comparator v6.0
- When I run Verilog simulation (post-NGDBuild, post-MAP, or post-PAR), "x"s appear in my output. For most simulators, "x" means "don't care" conditions. (This does not happen with VHDL simulation.)
Please see (Xilinx Answer 15808).

- When I compile the CORDIC behavioral model using Synopsys VHDL Analyzer (VHDLAN), the following failure occurs because Synopsys does not include the "IEEE.numeric_bit" library:
"Error: Analysis Parsing vhdl-481 during Synopsys VHDL Analyzer compilation"
Please see (Xilinx Answer 16114).

- 5.1i sp2 MAP, LogiCORE CORDIC v1.1 - MAP reports the following error when I place the CORDIC v1.1:
"ERROR:Place - Structured logic associated with an F6 configuration could not be placed."
Please see (Xilinx Answer 16161).

LogiCORE CIC v3.0
- The CIC v.3 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input.
Please see (Xilinx Answer 12480).

- On certain simulators, such as NCSIM and ActiveHDL, the output of the MAC FIR is always "x" (invalid) for the first N (number of coefficients) cycles of the filter.
Please see (Xilinx Answer 16120).

- The MAC FIR outputs incorrect results on the DOUT pin for behavioral and netlist simulations for certain parameters of the MAC FIR core.
Please see (Xilinx Answer 16162).

LogiCORE Multiplier v6.0
- 5.1i sp2 MAP, LogiCORE Multiplier v6.0 - MAP reports the following error when I attempt to pack a Multiplier core:
"ERROR:Pack:1134 - A collection of symbols which have restrictive placement or routing requirements..."
Please see (Xilinx Answer 16163).

LogiCORE Asynchronous FIFO v5.0
- 5.1i ECS and XST LogiCORE Async FIFO v5.0 - When I use ECS, XST errors report that the PORT for an Asynchronous FIFO cannot be found.
Please see (Xilinx Answer 16232).


- When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators report a number of warnings and errors.
Please see (Xilinx Answer 12630).

- When XilinxCoreLib files are compiled using Cadence NCVHDL, simulators report a number of warnings and errors.
Please see (Xilinx Answer 14185).

- Pre-compiled XilinxCoreLib libraries for ModelSim Xilinx Edition II (MXE) are currently undergoing testing. Once testing has been completed, the pre-compiled libraries will be available at:
AR# 16109
Date 03/05/2003
Status Archive
Type General Article