General Description: During timing simulation, Xs are generated by asynchronous portions of my design.
Typically, these Xs appear because of setup or hold errors. The X that is generated when these errors occur can be disabled by the ASYNC_REG constraint. (Please see (Xilinx Answer 15969) for more information.)
Another possible cause is a bug that affects the way a muxing structure is currently modeled in the timing simulation netlist. In the netlist, several muxes are cascaded together, and the logic on the select lines is such that one of the mux inputs never logically affects the output of the cascaded muxes; therefore, this input is left unconnected.
However, the timing on the select lines allows the X from the unconnected input to propagate through the muxes, and a very small X pulse is outputted from the cascaded muxes. In most cases, this X does not affect the simulation. In synchronous portions of a design, this X will never affect the output; however, in asynchronous portions of the design, this X may be registered in some circumstances. This X cannot be disabled by the ASYNC_REG constraint, as an X input to a register will always cause the output to be X if the X is present on the input when the clock transition occurs.
The correct modeling structure would be to tie off the unconnected input to VCC. The change on the output of the cascaded muxes may still cause a setup or hold violation, as this is an asynchronous portion of the design, but the X output can be disabled with the ASYNC_REG constraint if the input is a valid 1 or 0.
This problem is scheduled to be fixed in the 5.2i software, which will be available in late February, 2003.