General Description: In some cases, the clock delays in the SDF do not match the delays reported by TRCE. There is a difference in how TRCE and NGDAnno use the speed files, causing a large positive clock skew to be added between two registers. This makes the simulation much more optimistic than TRCE, which allows the simulation to be run with higher clock frequencies than what TRCE reports.
TRCE does not currently report positive clock skew, so the simulation will always be a little more optimistic than the TRCE report, but this difference makes the simulation much more optimistic. The positive clock skew can be as much as 500 ps.