General Description: When I use Synplify as the synthesis tool and attempt to use a KEEP_HIERARCHY constraint, the ports of the hierarchical blocks in the simulation netlist are not preserved correctly. In some cases, extra ports with a "\$s_annotrans_" prefix are added to the port list.
For example, assume that a module should only have four ports: clk, reset, data_out, addr.
The module should look like:
module test ( data_out, addr, clk, data_out);
Instead it, looks like:
module test ( data_out, addr, clk, data_out, \$s_annotrans_addr);
Note the extra port named "\$s_annotrans_addr". Additionally, the actual "addr" port is not connected.