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AR# 16232

6.1i COREGen - Async or Sync FIFO ECS schematic symbol has the wrong case, and XST errors report that the ports cannot be found


Keywords: XST, ECS, LogiCORE, Asynchronous, Async, FIFO, schematic, symbol, port, Verilog

Urgency: Standard

General Description:
When I use an Async or Sync FIFO with ECS (in a Verilog synthesis/Simulation flow), the schematic symbol has the wrong case; this causes XST errors to report that the ports cannot be found.


The characters of the ECS schematic symbol created for the FIFO are written in different cases for the ports than those used by the wrapper file for the FIFO. Because the wrapper file is necessary for simulation and synthesis, the fact that Verilog is case-sensitive causes a problem.

To avoid this error, modify the wrapper so that the ports are all written in uppercase characters.
AR# 16232
Date 01/08/2006
Status Archive
Type General Article