When I run a design through Timing Analyzer, the summary of the constraint says that no timing errors were detected. However, the minimum time listed for the constraint is more than what I requested.
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 30 nS HIGH 50.000000 % ;
"414065 items analyzed, 0 timing errors detected.
Minimum period is 33.286ns."
There is a request for a minimum period of 30 ns, and the tools report a minimum period of 33.286 ns. Why is this not flagged as a timing error?
This problem can occur when a two-phase path with unrelated PERIOD constraints is applied to the source and destination registers even though they share the same clock signal. This usually occurs if the PERIOD constraints are not applied in a typical way using the TNM_NET constraint. You can work around this problem by ensuring that registers sharing a clock signal have related constraints.
The tools have been modified to perform a more detailed check on cross-clock domain paths.
This problem is fixed in the latest 5.1i Service Pack, available at:
The first service pack containing the fix is 5.1i Service Pack 3.