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AR# 16272

5.1i ISE Install - Service Pack 3 Release Notes / README

Description

Keywords: Service Pack, 3, Solaris, UNIX, PC, software, update, 5.1i, SP3

This README contains the Release Notes for the 5.1i Service Pack 3. The Release Notes include installation instructions and a list of the issues that are fixed by this Service Pack.

Solution

A successful installation of Xilinx ISE 5.1i Service Pack 3 will update your software version number to 5.1.03i.

NOTE 1: The destination directory specified during the set-up operation must contain an existing Xilinx ISE 5.1i installation. Only existing files are updated. Any new device support not previously installed should first be installed from the Xilinx ISE 5.1i CD before adding Service Pack 3.

NOTE 2: The Xilinx ISE 5.1i environment variable should be set before commencing the installation of Service Pack 3.

Download installation instructions for PC:
1. Download 5_1_03i_pc.exe from:
http://support.xilinx.com/support/techsup/sw_updates/.
2. Run "5_1_03i_pc.exe".

Download installation instructions for Solaris Workstation:
1. Download 5_1_03i_sol.tar.gz from:
http://support.xilinx.com/support/techsup/sw_updates/
2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
gzip -d 5_1_03i_sol.tar.gz
tar xvf 5_1_03i_sol.tar

3. Run "5_1_03i_sol/setup".

BitGen

5.1i iMPACT - Verification of a Virtex-II/Pro device causes "ERROR:Bitstream:63 - Trying to read past end of bitstream"
(Xilinx Answer 15958)

CompXLib

5.1i CompXLib - "ERROR:compxlib[init]:2 - unable to remove file \tmp\.xlog"
(Xilinx Answer 15675)

CPLD

5.1i CPLD XC9500XL/XV - The "Terminate Float' option does not create a JEDEC file with bus-hold disabled.
(Xilinx Answer 15069)

ECS

5.1i ECS - During a schematic check, "no load" and "no source" errors are reported when the driven net is part of a complex bus.
(Xilinx Answer 15814)

5.1i ECS - I cannot choose symbols at the bottom of the symbol list.
(Xilinx Answer 16024)

Floorplanner

5.1i Floorplanner - Floorplanner reports numerous warning messages on multiple area group constraints before opening.
(Xilinx Answer 15583)

5.1i Floorplanner - The "Group" function for area group constraints does not work, resulting in "ERROR:NgdBuild:753..."
(Xilinx Answer 15705)

5.1i Floorplanner - "Unable to find sym <inst>" appears when cross-probing from Timing Analyzer fails to locate a component.
(Xilinx Answer 15995)

5.1i Floorplanner - An invalid Floorplanner NCF file causes "ERROR:Pack:311 / 312 - Unable to resolve the conflicts between two or more collections..."
(Xilinx Answer 16128)

HPrep6

5.1i CoolRunner-II Hprep6 - "Warning: CPLD:814 - Programming output (JEDEC) for device type XC2Cxxxx is not supported in this release."
(Xilinx Answer 12104)

5.1i CPLD Hprep6 CoolRunner-II - VREF I/O Standards (HSTL-1, SSTL2-1, SSTL 3-1) do not work on the device.
(Xilinx Answer 15720)

iMPACT

5.1i iMPACT - XC18V01/512/256 SVF programming fails.
(Xilinx Answer 14193)

System ACE MPM Update - 4.2i/5.1i iMPACT - Erase or Verify fails when I attempt to program the System ACE MPM Flash.
(Xilinx Answer 15017)

5.1i sp2 iMPACT - "ERROR:iMPACT:1111 - Can't locate bsdl file xc2v250_bg352.bsd"
(Xilinx Answer 15821)

5.1i iMPACT, System ACE CF - When I attempt to program the JTAG chain using the .ace file, configuration fails.
(Xilinx Answer 15956)

5.1i sp2 iMPACT - The GUI does not launch and reports "iMPACT launched in a write protect directory - please re-launch iMPACT" (Solaris)
(Xilinx Answer 15968)

5.1i iMPACT - The SVF file does not erase CoolRunner (XPLA3) devices.
(Xilinx Answer 16309)

MAP

Virtex-II, DCM - The use of negative, FIXED-mode phase shift requires a work-around or a positive PHASE_SHIFT value (DPS).
(Xilinx Answer 13349)

5.1i Virtex-II MAP - MAP's Logical DRC flags a nonexistent error regarding FDDRRSE input signals.
(Xilinx Answer 15232)

5.1i Virtex-II MAP - "FATAL_ERROR:MapHelpers:mhcv2devpkg.c:51:1.12"
(Xilinx Answer 15729)

5.1i Virtex-II MAP - Unchanged area groups are unplaced in an incremental run when the compression factor is introduced.
(Xilinx Answer 16278)

5.1i Virtex-II MAP - The RLOC constraints of RAM and a flip-flop fail, but the packer performs the same pack by default.
(Xilinx Answer 16279)

5.1i Virtex-II MAP - In fixed mode, DCM incorrectly requires all PS* inputs to be tied to GND.
(Xilinx Answer 16280)

5.1i Virtex-II MAP - "ERROR:DesignRules:590 - Blockcheck: Dangling DYMUX input..."
(Xilinx Answer 16286)

NGD2VER

5.1i sp2 ModelSim, NGD2VER - Errors: "Failed to open SDF - Fatal: (vsim-SDF-3445) Failed to parse SDF file."
(Xilinx Answer 16182)

NGDAnno

5.1i sp2 Timing Simulation, DCM, Verilog - The DCM does not lock during a Verilog timing simulation.
(Xilinx Answer 16152)

5.1i sp2 NGDAnno - "Errors: EXCEPTION:Sdm:sdm_hashtable - FATAL_ERROR:Anno:Port_Main.h:126:1.21..."
(Xilinx Answer 16177)

5.1i sp2 Timing Simulation, NGDAnno, Virtex-E - Timing Simulation does not fail when the maximum clock frequency reported by TRCE is exceeded.
(Xilinx Answer 16178)

5.1i sp2 NGDAnno, NGD2VHDL, NGD2VER, KEEP_HIERARCHY - In hierarchical blocks, extra ports with "\$s_annotrans_" are created and a number of ports are left floating.
(Xilinx Answer 16181)

NGDBuild

5.1i NGDBuild - The name "Xilinx" in the working directory path name causes errors.
(Xilinx Answer 16275)

PACE

5.1i PACE - PACE crashes, reporting "WARNING:Portability:111 - Message file...wasn't found/".
(Xilinx Answer 16315)

Packages

5.1i sp3 Virtex-II Packages - The XC2V2000-BG728 and XC2V8000-BF957 device and package combinations are not available.
(Xilinx Answer 16319)

PAR

5.1i Virtex-II PAR - "ERROR:Place:249 - Automatic clock placement failed."
(Xilinx Answer 15809)

5.1i Virtex-II Pro, PAR - "ERROR:Place - BREF CLK N brefclk2 must be placed in site C13, but cannot be placed there..."
(Xilinx Answer 15984)

5.1i Virtex-E PAR - Problems are seen with local clock routing.
(Xilinx Answer 16102)

5.1i Virtex-II Pro - PAR reports a large delay for a clock net in a GT10 design.
(Xilinx Answer 16288)

5.1i Virtex-II PAR - Change in how VCC connections are routed for Partial Reconfiguration designs.
(Xilinx Answer 16289)

5.1i Virtex PAR - PCI 64/66 designs fail to meet timing due to the PAR routing behavior of PCI_CE net.
(Xilinx Answer 16290)

5.1i PAR - Guided PAR component and signal name matching statistics are sometimes incorrect.
(Xilinx Answer 16293)

5.1i Vitex-E PAR - MPPR results do not vary unless the extra effort (-xe 1) option is used.
(Xilinx Answer 16296)

5.1i Spartan-II PAR - A crash occurs during Guided PAR.
(Xilinx Answer 16298)

Project Navigator

5.1i ISE - When I attempt to create a schematic symbol from a VHDL file, ISE reports "Can't read "ProcessName". No such variable ..."
(Xilinx Answer 15890)

5.1i ISE - Project Navigator is incorrectly passing a value for "Global Disable of X-generation for Simulation" (-xon).
(Xilinx Answer 15985)

Speed Files

5.1i Speed Files - "WARNING:Timing:2719 - The clock ref_clk has a low pulse width..."
(Xilinx Answer 16276)

5.1i Speed files - Spartan-II changed from speed file version 1.26 to 1.27, and Spartan-IIE changed from version 1.16 to 1.17.
(Xilinx Answer 16277)

Timing

5.1i Timing - DCM pulse width checks for Virtex-II are incorrect (false warnings are issued).
(Xilinx Answer 15769)

5.1i Timing - Cross-clock paths are not listed by the destination clock in the unconstrained path report.
(Xilinx Answer 16274)

TRCE

5.1i sp2 Trace (TRCE)/Timing Analyzer - A negative Tdcmino value causes hold errors in timing for the PSDONE path.
(Xilinx Answer 16052)

5.1i TRCE/Timing Analyzer - Timing Analyzer reports zero errors even though one constraint is not met.
(Xilinx Answer 16270)
AR# 16272
Date Created 12/02/2002
Last Updated 04/28/2006
Status Archive
Type General Article