We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 1633: XEPLD, XC7318, XC7336: nd100:[Error] (nd105, hi317) Could not map '<instance>' into a fast function block. (Fast Output Enables, FOE)
XEPLD, XC7318, XC7336: nd100:[Error] (nd105, hi317) Could not map '<instance>' into a fast function block. (Fast Output Enables, FOE)
Keywords: 7318, 7336, foe, fast function block, fast output enable, hi317, nd100, nd105
Upon implementing a XC7318 or XC7336 design the following errors may be encountered during the optimize stage of implementation:
nd100:[Error]Could not map '<instance>' into a fast function block macrocell. nd105:[Error]Device does not have enough Fast Output Enables to convert macrocell pterm enable into an FOE as required for fast function blocks. hi317:[Error]Invalid fast function mapping requirement found. Possibly there is too much logic declared as fast in your design.
This error is typically caused by a design which targets the XC7318 or the XC7336 and which uses more than two device output enables. Since the XC7318 and XC7336 have *only* Fast Function Blocks, the device may only have 2 output enables. This is because the output enables in Fast Function Blocks can come from one of two places, the FOE0 pin or the FOE1 pin. Even if the design generates an output enable signal internally, that output enable signal will still need to use one of these 2 FOE pins to get back into the device on an output enable line.
There are no product term output enables in Fast Function Blocks.
Therefore, if the design has an internally generated output enable(s), an FOE pin must be left free for each of those internally generated output enable(s).
Target a 7300 device that contains High Density Function Blocks such as the 7354 or larger device.
You may also try targeting an equivelent 9500 device.
Limit the number of output enables in the design to 2.
If the design contains an internally generated output enable(s), be sure that there is a corresponding FOE pin available for the signal to use to get onto the output enable line.
Was this Answer Record helpful?