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AR# 16340

LogiCORE Binary Counter v6.0 - Why does the behavioral simulation of Counter v5 or v6 result in 'X' as the counter output?


Keywords: unknown, X, ModelSim, MTI, behavioral, RTL, simulation, XILINXCORELIB, VHDL, ISE, coregen

Urgency: Standard

General Description:
Performing behavioral simulation of the Counter core using the Xilinx CoreLib models results in only unknowns ("X") as counter outputs.


The following are possible ways to work around this problem:

- Make sure you have all of the inputs assigned before clocking the counter.

- This problem occurs when HDL Bencher is used to generate the testbench. HDL Bencher starts the clock at '0' and it only remains there for a small fraction of the clock cycle before it is switched to '1'. This causes 'X' to be generated from the counter. You can workaround this problem by either modifying the testbench clock generation process or writing your own testbench.

- Connect the counter reset to the system reset, and reset the counter at the beginning of the simulation.
AR# 16340
Date 07/12/2007
Status Archive
Type General Article
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