We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 16355: 3.1/3.2 EDK : I specify Little Endian notation for a global port, but this becomes Big Endian notation in the VHDL
3.1/3.2 EDK : I specify Little Endian notation for a global port, but this becomes Big Endian notation in the VHDL
I specify global ports in an MHS file in little endian format (Myport[x:0]), either by directly editing the MHS file in XPS, or by using the System Settings dialog box. If I then run PlatGen or the "Generate Netlists" process, the global ports use the big endian format (Myport[0:x]) in the System_Stub.vhd and the System.vhd files.
To work around this issue, edit the system_stub.vhd and the system.vhd files so that the global ports are specified in the desired format.