We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16365

5.1i ECS - Schematic DRC reports errors for unconnected I/O ports/Schematic netlister reports "ERROR:DesignEntry:2 - Net "<port_name>" must be connected to pins or I/O ports"


Keywords: SCH2VHDL, SCH2Verilog, connected, I/O, IO, port, DesignEntry, schematic

Urgency: Standard

General Description:
If I place an I/O port on a schematic with no connections, the schematic DRC flags the unconnected I/O port with the following error:

"Error: Net "<port name>" needs to be connected to pins or I/O ports."

If I run any process on the schematic design in Project Navigator, the schematic netlister (SCH2VHDL or SCH2VERILOG) fails and reports the following error:

"ERROR:DesignEntry:16113 - Net "<port name>" needs to be connected to pins or I/O ports."


In the 5.1i software, schematic checks were added to prevent users from inadvertently leaving ports and nets unconnected. However, this causes problems for cases in which a user wishes to temporarily leave a port unconnected while testing other parts of the design.

In the 6.1i software, unconnected I/O ports will only be flagged with a warning by default. When the schematic check is run, the warnings will appear, but the HDL file will be created correctly.

In the 5.x ECS software, you may leave an I/O port unconnected in the schematic and prevent errors by connecting a buffer to the port with the opposite side of the buffer left unconnected.

The bit size of a BUF component may be changed to match the size of a port bus by changing the BUF instance so that it uses bus notation (e.g., to connect to a 4-bit port bus, change the instance name from "XLXI_5" to "mybuf(3:0)".)

For more information, please also see (Xilinx Answer 16113).
AR# 16365
Date 01/08/2006
Status Archive
Type General Article