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AR# 16418: ISE 5.2i - Known Issues for IP Cores (DSP, System Logic, Networking, Ethernet, PCI, PCI-X)
ISE 5.2i - Known Issues for IP Cores (DSP, System Logic, Networking, Ethernet, PCI, PCI-X)
This Answer Record contains known issues for using the ISE 5.2i implementation tools on designs with IP.
DSP and System Logic Cores
All cores provided with ISE 5.2i work with the ISE 5.2i implementation tools. Please do not install the 5.1i IP Update #1 (F_ip1) on the ISE 5.2i software.
- The SPI-4.2 (PL4) v5.2 is tested and works with ISE 5.2i.
- The SPI-4.2 (PL4) Lite v1.1 is tested and works with ISE 5.2i.
- The PL3 v3.0 is tested and works with ISE 5.2i.
- The FlexBus4 v1.0 is tested and works with ISE 5.2i.
Ethernet MAC Cores
- Gigabit Ethernet MAC with PCS/PMA v2.0, v2.1
- 10 Gigabit Ethernet MAC with XAUI v2.0, v2.1
The Ethernet MAC core versions listed above do not work in the 5.2i software because of changes in the port maps of the MGTs associated with BREFCLK in the 5.2i Xilinx UniSim library. Please use the 4.2i software with these cores.
If you must use the v2.0 and v2.1 cores with the 5.2i software, please contact Xilinx Customer Support to request a special build of these cores. Please see (Xilinx Answer 15533) for more details.
The v3.0 release of both cores (March 2003) is compatible with the 5.2i software.
The current v3.106 PCI core and v.5.56 PCI-X core work successfully (without any known software related issues) in 5.2iSP2. For non-software related known issues, see the core's Release Notes.
If you are using 5.2iSP3 and experiencing problems related to timing, please revert back to 5.2iSP2. Xilinx is aware of timing related issues when using the PCI and PCI-X LogiCOREs with 5.2iSP3 and is resolving the issue. The errors will most likely occur on the OFFSET IN/OUT constraints.
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