What software drivers are supported for the EMAC core, and what are the differences in driver support between the regular EMAC core and the MontaVista version?
The following driver support is available for the non-Lite 10/100 Ethernet MAC core:
- Layer 0, Layer 1, and VxWorks Layer 2 software drivers for the 10/100 (non-Lite) EMAC core developed by Xilinx.
- Layer 2 drivers from MontaVista that integrate the Xilinx Layer 1 driver into Linux (only interrupt driven mode is supported)
(Please refer to the note at the end of this for information on how to obtain MontaVista support.)
For the Lite core, only a Layer 0 driver is supported because the Lite core does not support interrupts or DMA.
- A Layer 0 Device Driver is a primitive driver for simple systems that provide basic operations such as register access.
- A Layer 1 Device Driver provides a more full-featured and robust driver (DMA, interrupts, etc.). Layer 1 drivers are typically used in embedded systems marketed without an RTOS. Layer 1 drivers do not tightly integrate with the network stack of the RTOS automatically.
- A Layer 2 Device Driver (also called an "adapter") is tightly integrated with a specific RTOS. It integrates the Layer 1 driver into the respective operating system (either VxWorks or MontaVista) (non-Lite core only).
Complete information on driver support for the various processor cores can be found in the EDK Documentation which comes with EDK. (See the section on Xilinx Drivers.)
- The Xilinx EMAC core is not compatible with any existing drivers for other EMACs.
NOTES on MontaVista Support:
- Customers interested in MontaVista driver support should contact MontaVista to purchase the MontaVista Linux development environment for PowerPC. This environment supports a variety of Xilinx Processor IP peripherals, including the OPB 10/100 Ethernet MAC.
As of 01/07/04:
The drivers that currently ship as part of the MontaVista Linux Professional 3.0 edition supports the OPB 10/100 EMAC in interrupt driven mode, i.e., with C_DMA_PRESENT = 1.
Improved interrupt mode performance and added support for SGDMA and the PLB 10/100 EMAC are targeted for Q2CY2004.