UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16650

Schematic - An unconnected pin on the startup block causes the error: "$/start/start.vhf",line 31: Error, CLK does not have an actual or default value"

Description

When I use the Virtex-II startup block with the Clk port unconnected, synthesis fails and the following error appears:

"$/start/start.vhf",line 31: Error, CLK does not have an actual or default value."

Solution

You can work around this problem in two ways:

1. Assign a default value (:= 'X') to the startup component ports.

2. Add an unconnected net to the CLK port of the startup block.

- Change the "Consider Undriven Nets as" setting in ECS by going to Edit -> Preferences -> Check. Change this setting from "Error" to "Warning".

AR# 16650
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article