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AR# 16725

5.2i CPLD TAEngine/Tsim CoolRunner-II - Outputs for HSTL-1, SSTL2-1, and SSTL3-1 use incorrect output delay adders

Description

Keywords: 5.1i, 5.2i, CPLD, CoolRunner-II,TAEngine, output, timing

Urgency: Standard

General Description:
Outputs configured as SSTL2-1, SSTL2-3, and HSTL-1 use incorrect timing components for the output buffer delay.

Example:
The dout<0> output is configured as type SSTL2-I, but the detailed timing summary shows that dout<0> uses the LVCMOS25 output adder instead of the ToutSS2 output adder.

From: clk - : 0.0ns (0.0ns)
Thru: clk.GCK tGCK : 1.6ns (1.6ns)
Thru: dout<0>.Q tCOI : 0.2ns (1.8ns)
To: dout<0> tOUT + tOUT25 : 3.5ns (5.3ns)

This behavior occurs for the SSTL3-1 and the HSTL-1 IO Standards as well.
HSTL-1 uses no timing adder when it should use ToutHS1.
SSTL3-1 uses Tout33 when it should use ToutSS3.

Solution

This problem is fixed in the latest 5.2i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 5.2i Service Pack 2.
AR# 16725
Date Created 09/03/2007
Last Updated 08/13/2009
Status Archive
Type General Article