We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16773

5.2i HDL Bencher - Additional clock signals may not be added to a testbench waveform


Keywords: Port, Ports, Signals, clock, add, Bencher, module, TBW

Urgency: Standard

General Description:
My existing design source file has an associated .tbw (testbench waveform) file. If I add additional port signals to the source, the testbench waveform can be updated to include the additional signals. However, if a new signal is a clock input, the testbench waveform cannot be updated to incorporate the signal as a clock. How can I add additional clocks to a testbench waveform?


Additional clock signals cannot currently be added in HDL Bencher. New signals may be added as inputs, outputs, or bidirectionals. You may add a signal and assign a pattern; however, the signal transitions would have to take place relative to an existing clock, and there is no way to associate additional signals to the newly added signal.

To incorporate a new clock, you must create a new .tbw file in a testbench waveform.
AR# 16773
Date 02/07/2006
Status Archive
Type General Article
Page Bookmarked