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AR# 16777

LogiCORE SPI-4.2 (POS-PHY L4) - Virtex-II Pro I/O banking rules for status bits (RSClk, RStat, TSClk, TStat)

Description

General Description: 

This Answer Record describes the best method for choosing SPI-4.2 (PL4) status bits pins in Virtex-II Pro devices. 

 

NOTE: For more information on LVTTL support in Virtex-II Pro, please see (Xilinx Answer 14965) and Module 2 of the Virtex-II Pro data sheet: Detailed Functional Description: FPGA -> Digitally Controlled Impedance: 

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=/Data+Sheets/FPGA+Device+Families/Virtex-II+Pro&iLanguageID=1
 

Please see (Xilinx Answer 12420) for SPI-4.2 (PL4) v5.2 Known Issues.

Solution

Sink Status Channels 

Sink Status Channel outputs are not pin-locked. However, Xilinx recommends the following guidelines: 

 

LVDS Status Channel 

- Place RSClk, RStat_P(0) and RStat_P(1) in Bank 7 with a Sink Core. 

 

LVTTL Status Channel with Bank 7 VCCO = 3.3V 

- If Bank 7 VCCO can be set to 3.3V, the 3.3V LVTTL outputs and 2.5V LVDS inputs can reside together in Bank 7.  

- VCCAUX must be set to 2.5V. 

- LVDS_DCI cannot be used with VCCO=3.3V. 

 

LVTTL Status Channel with Bank 7 VCCO = 2.5V 

- Place RSClk, RStat(0), RStat(1) in a 3.3V bank. 

 

Source Status Channels 

Source Status Channel outputs are not pin-locked. However, Xilinx recommends the following guidelines: 

 

LVDS Status Channel 

- Place TStat_P(0) and TStat_P(1) in Bank 6 with a source core. 

 

LVTTL Status Channel 

- Place TStat(0), TStat(1) in a 3.3V bank. 

- Note that TSClk must be placed on a clock pin.

AR# 16777
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article