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AR# 16785

v1.5 Aurora 401 Reference Design - The FIFO_ERR and CHANNEL_UP signals become "X" in VHDL simulation


The FIFO_ERR and CHANNEL_UP signals become "X" in a simulation of the VHDL model of an Aurora 401 design.


This is because of a problem with the VHDL Vital model for the FDRSE. The issue was fixed in version 1.6 of the Aurora reference design (a different model is used). 


The FDRSE problem will be fixed in the 6.1i software, as Xilinx will move to the use of behavioral models rather than Vital.

AR# 16785
Date 05/15/2014
Status Archive
Type General Article
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