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AR# 16808

6.1i XST - Casex statement causes incorrect logic implementation


Keywords: ISE, 5.1, Verilog, synthesis, simulation

My Verilog code uses a casex statement, and I use XST to synthesize the code. When I compare the behavioral simulation result of my code to the post-synthesis simulation results, they do not match.


This issue is fixed in ISE 7.1i
AR# 16808
Date 03/05/2006
Status Archive
Type General Article
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