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AR# 16830

Virtex-II Pro, Virtex-4 ,Virtex-5 - Can I put LVDS or LVPECL I/O in a 3.3V bank? Can I interface with 3.3V LVDS or LVPECL?

Description

Virtex-II FPGA provides two options for powering LVDS drivers: 2.5V and 3.3V (both have identical electrical characteristics). Is this possible with Virtex-II Pro, Virtex-4, and Virtex-5 FPGA? Can I put LVDS or LVPECL I/O in a 3.3V bank?

Solution

Virtex-II Pro, Virtex-4, and Virtex-5 devices support only LVDS_25 and LVPECL_25. As a result, LVDS_33 and LVPECL_33 I/O buffers are not available for instantiation.

The differential input buffers are powered by VCCAUX and are not VCCO-dependent. Consequently, you can put LVDS_25 and LVPECL_25 input buffers in a 3.3V bank; the software does not report errors, and the device is not damaged. In this case, the input specifications are as specified for LVDS_25 and LVPECL_25.

While the differential input buffer itself is not VCCO-dependent, there are some things to be aware of:

- If the Vih of the incoming signal exceeds VCCO by ~0.5V, the signal will be clamped. This could affect proper reception of the differential signal.
- If the LVDS_25_DT receiver is used (Virtex-II Pro) or the DIFF_TERM attribute is applied (Virtex-4 and Virtex-5), the internal termination will be dependent on VCCO. For more information, see (Xilinx Answer 20004).

Differential output buffers must be put in a 2.5V bank for Virtex-II Pro, Virtex-4, and Virtex-5 because the output buffers are powered by VCCO, and output specifications are VCCO-dependent. Instantiating an LVDS_25/LVPECL_25 output buffer in a 3.3V bank causes a software error.

To interface from a 3.3V differential driver to the Virtex-II Pro, Virtex-4, and Virtex-5 2.5V LVDS/LVPECL input, the output specifications of the driver must be within the Virtex-II Pro, Virtex-4, and Virtex-5 LVDS/LVPECL input specifications. If the specifications match, you can use the standard input termination. If the specifications do not match, the termination might need to be adjusted and an IBIS/SPICE simulation must be performed to determine the optimal termination scheme.

LVDS and LVPECL specifications are available in the "DC and Switching Characteristics" section of the data sheets.

Virtex-II Pro Data Sheet

http://www.xilinx.com/support/documentation/virtex-ii_pro_data_sheets.htm

Virtex-4 Data Sheet

http://www.xilinx.com/support/documentation/virtex-4_data_sheets.htm

Virtex-5 Data Sheet

http://www.xilinx.com/support/documentation/virtex-5_data_sheets.htm

The recommended resistor termination is available in the User Guides:

http://www.xilinx.com/support/documentation/user_guides.htm

Virtex-II Pro

Select Virtex-II Pro under FPGA Device Families -> Virtex-II Pro Platform FPGA User Guide, and go to Design Considerations -> LVDS I/O or LVPECL I/O.

Virtex-4

Select Virtex-4 under FPGA Device Families -> Virtex-4 User Guide -> SelectIO Resources -> Specific Guidelines for Virtex-4 I/O Supported Standards -> LVDS or CSE differential LVPECL.

Virtex-5

Select Virtex-5 under FPGA Device Families -> Virtex-5 User Guide -> SelectIO Resources -> Specific Guidelines for Virtex-5 I/O Supported Standards -> LVDS or differential LVPECL.

AR# 16830
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
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