To create the ADD8, follow these steps: 1. Create a New Source and select VHDL or Verilog module. 2. Copy and paste the example inference into a VHDL or Verilog source file. 3. In the Processes window, expand Design Entry Utilities and double-click Create Schematic Symbol. 4. Open the schematic source for the project, and in the Symbols list, click the project library. 5. The ADD8 component you created should appear in the bottom window. You can place it in your schematic.
In general, this error will occur when any lower-level module is not available to XST. If the module in question is a user-created sub-module, make sure that the HDL file that contains the description of the module (even if it is just the module declaration for black box instantiation) has been added to the XST project.