The Interrupt Status bit, which is bit 3 of the Status register or CSR bit 19, is behaving opposite of what it should. This bit reflects the state of the interrupt in the device, and it should be 1 if the device is asserting the interrupt and 0 otherwise. However, it is a 0 when the core is asserting the interrupt and a 1 otherwise.
This issue has been corrected. The first build showing this fix is release 3.106.