Why does the PLB Arbiter require three cycles to perform arbitration?
The Xilinx PLB Arbiter requires three cycles to perform arbitration because it was necessary to insert a pipeline or register stage in the arbiter to have a reasonable Fmax. This is a tradeoff of latency for overall clock frequency. However, note that this one cycle of latency is only incurred during the address phase of the transaction. Read and write address phases can overlap since the PLB has separate read/write data buses.