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AR# 16930

5.2i IP2 CORE Generator - Known Issues for CORE Generator in 5.2i IP Update #2 (also referred to as 5.2i IP2 or F_IP2)


General Description:

This Answer Record contains known issues addressed in the 5.2i IP Update 2 (also referred to as 5.2i IP2 or F_IP2).



Software Compatibility

Acrobat Reader Requirement

Acrobat Reader Version 4 or later must be installed to view core data sheets. You can download the latest Acrobat software from the following Adobe site:


Windows 2000/XP

- If you use a Windows platform, Xilinx recommends that you use the "High Color" setting for your display.

Please see (Xilinx Answer 12372).

- The CORE Generator GUI is not displayed in the Windows task bar when I double-click the XCO file in an ISE project.

Please see (Xilinx Answer 11386).

- The CORE Generator GUI pages are out of sequence when I cycle through the options for a core.

Please see (Xilinx Answer 16191).


- Clicking on the Web Browser button does not open Netscape on Solaris and the following message is reported:

"Netscape: Couldn't find our resources?"

Please see (Xilinx Answer 11771).

- CORE Generator does not work with Netscape 4.72 when it is launched from Project Navigator on Solaris.

Please see (Xilinx Answer 14793).

Xilinx Implementation Software Issues

When I import a design from the 3.1i software, "port mismatch " and "unconnected ports" messages are reported during simulation and implementation.

Please see (Xilinx Answer 13062).

Updates Installer Tool

- The Updates Installer Tool has been disabled for the remainder of the 5.x release. A problem found late in the 5.2i release allowed the installation of IP updates that were incompatible with the installed Xilinx software version.

For information on the latest available CORE Generator IP Updates, refer to the Xilinx Software Updates and follow the instructions for downloading and installing these updates manually:


- The Updates Installer Tool cannot be used to install cores that have been captured by the IP Capture Tool.

Please see (Xilinx Answer 14183).

- The installer may take several hours or the process seems to hang.

Please see (Xilinx Answer 12544).

IP Capture Tool

- When I use the IP Capture tool, the following error is reported:

"ERROR: Cannot open file <./XilinxCoreLib/vhdl_analyze_order> for writing. No analyze order list will be generated."

Please see (Xilinx Answer 14850).

Other Known Issues

- An "Update Project" dialog box appears when I open a project with multiple repositories.

Please see (Xilinx Answer 12345).

- XST synthesis fails and the following error is reported:

"ERROR: SimGenerator: Failure of Sim to implement customization parameters core decode_810".

Please see (Xilinx Answer 14684).

IP Known Issues

- LogiCORE SPI-4.2 (PL4)

When SPI-4.2 (PL4) v5.2 core is generated with CORE Generator 5.2i with the IP Update 2 installed, there will be an error when trying to simulate the FIFO loop-back example in VHDL. The error is reported from the simulator during the compilation of the pl4_src_top.vhd and pl4_snk_top.vhd files. The simulate_mit.do simulation script does call for these two files.

Please see (Xilinx Answer 17019).

- LogiCORE Asynchronous FIFO v5.1

What has changed in Asynchronous FIFO v5.1? (Verilog model behavior has changed significantly.)

Please see (Xilinx Answer 16804).

- LogiCORE 8b/10b Encoder v4.0

When 8b10b Encoder v4.0 is generated for Virtex and type set to Block RAM, the core will give incorrect results on the DOUT, DOUT_B, and DISPOUT when behavioral simulation is run for both VHDL and Verilog. The netlist simulation (post-NGDBuild, post-MAP, and post-PAR) or the design in the hardware produces different results than the behavioral simulation.

Please see (Xilinx Answer 16986).

- DA FIR v7.0, DDC v1.0 GUI, and MAC FIR v1.0

In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.

Please see (Xilinx Answer 14202).

- LogiCORE Comparator v6.0

When I run Verilog simulation (post-NGDBuild, post-MAP, or post-PAR), "x"s appear in my output. For most simulators, "x" indicates a "don't care" condition. (This does not occur with VHDL simulation.)

Please see (Xilinx Answer 15808).

- LogiCORE CIC v3.0

The CIC v.3 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input.

Please see (Xilinx Answer 12480).

- LogiCORE Asynchronous FIFO v5.0

5.1i ECS and XST LogiCORE Asynchronous FIFO v5.0. When I use ECS, XST issues an error that the port for an asynchronous FIFO cannot be found.

Please see (Xilinx Answer 16232).

- LogiCORE XFFT v2.0, ReedSolomon v4.0, Interleaver v2.0

5.2i PAR and LogiCORE XFFT v2.0 . PAR reports a warning when the "Create RPM" option is used.

Please see (Xilinx Answer 16931).

- LogiCORE MAC-FIR v3.0

5.2i PAR and LogiCORE MAC-FIR v3.0 . PAR takes a long time to route Spartan-3 MAC-FIR core.

Please see (Xilinx Answer 16932).

Simulation Known Issues

- When XilinxCoreLib files are compiled using Synopsys VSS or VCSi, simulators report a number of warnings and errors.

Please see (Xilinx Answer 12630).

- Pre-compiled XilinxCoreLib libraries for ModelSim Xilinx Edition II (MXE) are currently being tested. Once testing is complete, the pre-compiled libraries will be available at:

AR# 16930
Date 07/28/2010
Status Archive
Type General Article
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