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AR# 16946

LogiCORE SPI-4.2 (POS-PHY L4) - What do the different Phase Alignment signals mean? ( PhaseAlignRequest / PhaseAlignComplete / PhaseAlignEn / PhaseAlignErr)

Description

General Description:

What do the different Phase Alignment signals mean and how are they used? The different signals that are available are:

PhaseAlignEn

PhaseAlignRequest

PhaseAlignComplete

PhaseAlignErr

Solution

Dynamic Alignment:

NOTE: The Dynamic Phase Alignment functionality (per-bit deskew and the behavior of PhaseAlign*) can be verified only in Timing Simulation. However, all other functionality can be verified in Functional Simulation. Please refer to (Xilinx Answer 15436) for more details.

PhaseAlignEn (input):

Not used in Dynamic Phase Alignment. Tie this signal to '0'.

PhaseAlignRequest (input):

Active high signal that requests the phase alignment of the data (RDat/RCtl) to the clock (RDClk). This signal can be asserted only when the SnkOof and PhaseAlignComplete are asserted. When this signal is asserted, training patterns must be received on the RDat/RCtl data bus. Please see (Xilinx Answer 15442) for more details.

PhaseAlignComplete (output):

Active high signal that indicates that the phase alignment is complete

PhaseAlignErr (output):

Not used in Dynamic Phase Alignment. The output should be ignored.

Static Alignment:

PhaseAlignEn (input):

Not used in Static Alignment. Tie this signal to '0'.

PhaseAlignRequest (input):

Not used in Static Alignment. Tie this signal to '0'.

PhaseAlignComplete (output):

Not used in Static Alignment. The output should be ignored.

PhaseAlignErr (output):

Not used in Static Alignment. The output should be ignored.

For details on setting fixed phase shift, please refer to (Xilinx Answer 16112)

AR# 16946
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article