AR# 16986: LogiCORE 8b10b Encoder v4.0 - Virtex, Block RAM-based exhibits incorrect behavior on DOUT, DOUT_B and DISPOUT
LogiCORE 8b10b Encoder v4.0 - Virtex, Block RAM-based exhibits incorrect behavior on DOUT, DOUT_B and DISPOUT
General Description: When I use the 8b10b Encoder v4.0 with Virtex and type set to Block RAM, incorrect results are reported on the DOUT, DOUT_B, and DISPOUT when I run behavioral simulation for both VHDL and Verilog. The netlist simulation (post-NGDBuild, post-MAP, and post-PAR) or the design in the hardware produces different results than the behavioral simulation.
When you generate the 8b10b Encoder core for Block RAM-based Virtex, the start-up state for the core is all 0's, as defined in the Data Sheet. This is due to the limitation of Virtex Block RAM. The problem occurs because the behavioral simulation model does not represent this limitation. It incorrectly sets the initial state to the user-defined state defined in the GUI or in the XCO. This problem does not occur with Virtex-II devices or for the LUT-based 8b10b Encoder.
You can work around this issue in two ways:
1. In the GUI, select "FORCE CODE". Enabling the "FORCE CODE" input automatically corrects the initial start-up state even though the input is tied to the 8b and is never used. However, Xilinx recommends that you use this input and tie it to a synchronous reset.
2. If you do not want the "FORCE_CODE" input, you can manually modify the COREGen-generated wrapper file <component_name>.v or <component_name>.vhd and set the values as follows: c_force_code_disp => 8b's, c_force_code_disp_b => 8b's, c_force_code_val => "0000000000", c_force_code_val_b => "0000000000",