The Spartan data sheets specify the following two methods for debugging configuration data:
- Read-back verify
- Read capture
Using 4.2i iMPACT, I can perform a read-back verify. How can I perform a read-back capture?
NOTE: The Spartan/-XL debug flow is useful when you want to configure and debug your design prototype. You can use the Hardware Debugger and the XChecker cable for this task. This method does not require external storage for configuration data or an external clock to synchronize the configuration process. The XChecker cable contains static RAM and an internal oscillator circuit for clock generation. The FPGA is configured in slave serial mode. For more information on this mode, refer to the slave serial mode description in the "Configuration and Test" section in the Spartan/-XL data sheet.
4.2i iMPACT does not support read-back capture. Please note that you need to use the Hardware Debugger tool in ver 3.3.08i (or earlier) of the Xilinx Foundation Series to perform a read-back capture. The following steps are required to perform this task:
1. Instantiate the READBACK symbol in your schematics or HDL-based design.
For more information on the READBACK symbol, refer to the "Configuration and Test" section in the Spartan/-XL data sheet.
2. Create the EDIF netlist for your design.
3. Implement your design to generate the LL and bit files as follows:
a) Set the read-back clock to CCLK, and check the field for "Enable Bitstream Verification" and "In-Circuit Hardware Debugging" in the Configuration Options window to use the internal clock in the FPGA to synchronize the read-back data and create an LL file for read-back. The Hardware Debugger uses this file for the read-back operation.
b) Implement your design using the Xilinx Foundation/Alliance implementation tools to create the bitstream. For more information on implementing your design, refer to the "Implementation Options" chapter in the Design Manager/Flow Engine Reference/User Guide.
4. Set the XChecker cable connections as follows:
a) Make sure the mode pin(s) are set for slave serial mode. Although these pins have a weak pull-up resistor during configuration, Xilinx recommends attaching an external pull-up of 4.7 KW to make sure these pins are not floating.
b) Connect the cable connectors 1 and 2 to the target system. This setup is used to perform synchronous debugging in which the cable is used to control the external system clock and the logic states of your design. The XChecker cable needs 5V DC power, which is drawn from the target system. The required power supply is 5V DC for a system with Spartan devices and 3.3V DC for a system with Spartan-XL devices. Since the XChecker cable must be powered with only a 5V supply, a separate 5V supply can be used for the Spartan-XL system or an 3.3V XChecker adapter (Order Number: HW-XCH3V) can be used that accepts 2.9-5.25V DC as input and provides the output stepped up to the 5V needed by the cable.
(c) Power up the board using the DC power supply.
(d) Invoke Hardware Debugger from the Design Manager window. For a description of XChecker pin connections, refer to Tables 4_3 and 4_4 in the "Connecting your Cable" chapter of the Hard-ware Debugger Reference/User Guide.
NOTE: The INIT pin on the connector is marked as INIT by mistake. For XChecker cable connections, refer to the 3.1i Hardware User Guide at:
5. Configure and debug using the Hardware Debugger as follows:
a) Configure the device using the Hardware Debugger software. Set the synchronous debug mode, clock options, trigger type settings and the signals to display.
b) Perform the device read-back and verify operations using the software. For more information on these operations, refer to the "Programming a Device" or a "Daisy Chain and Debugging a Device" chapters in the Hardware Debugger Reference/User Guide or the online help, which is available in the Hardware Debugger software.