What are the jitter requirements for the system clock (sys_clk) and receive clock (rx_clk) when using the LogiCORE RapidIO PHY?
The system clock and the receive clock are both fed into a DCM inside the core. So the jitter specifications for these input clocks are the same as the jitter specifications for the DCM. Also, consult the RapidIO Specification for information on system clocking related to jitter, skew, and the system timing budget. A copy of the RapidIO specification can be obtained from:
The DCM requirements are in the device data sheets at: