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AR# 17006

CPLD XC9500 CoolRunner XPLA3, CoolRunner-II - Are there minimum timing values for Xilinx CPLDs?


Are there minimum timing values for Xilinx CPLDs? The data sheet only shows worst case delays.


To determine a path minimum, a rule-of-thumb is to look at the fastest speed grade part for the given density and find the maximum specification in the data sheet. A minimum should be no less than 1/4 of the maximum value.


To determine the clock-to-out path for a CoolRunner-II 384 macrocell device in a -10 speed grade, follow these steps:

1. Open the XC2C384 data sheet and look for Tco (clock-to-out).

2. Look up Tco for the fastest speed grade (-7 is fastest in this density).

3. Multiply this value by 0.25 to find the minimum value for Tco.

The reason that you must use the fastest speed grade is that a part might be sorted into a slower speed grade because of only one timing path that does not meet the faster speed requirements.

For other common CPLD questions, see the CPLD FAQ at (Xilinx Answer 24167).

AR# 17006
Date 12/15/2012
Status Active
Type General Article