UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17055

12.1 Timing - "Warning: The following connections close cycles, and some paths through these connections may not be analyzed."

Description

When I use the Timing Analyzer on certain signals, the following message occurs: 

 

"Warning: The following connections close cycles, and some paths 

through these connections may not be analyzed." 

 

Signal Driver Load  

-------------------------------- ---------------- ----------------  

iupa[1] SLICE_X83Y69.Y SLICE_X89Y69.F4 

iupa[2] TBUF_X72Y68.O SLICE_X78Y91.G1 

iupa[4] TBUF_X72Y70.O SLICE_X78Y72.G4

Solution

One way to analyze paths in a loop (similar to how paths between non-synchronous elements are analyzed) is as follows: 

 

1. Make the starting point net and end point net in the loop synchronous by using TPSYNC. You can read about TPSYNC in the "Constraints Guide" in the "Xilinx Constraints T" section. The "Constraints Guide" is available at: 

http://www.xilinx.com/support/software_manuals.htm
 

Also, the "6.xi Timing and Placement Constraints" tutorial contains useful information, including an application example of TPSYNC. This tutorial is available at: 

http://www.xilinx.com/support/techsup/tutorials/index.htm
 

2. Write a FROM:TO constraint between the two new TPSYNC points and only analyze that FROM:TO constraint in Timing Analyzer to see it. The FROM:TO constraint is well documented in both the "Constraints Guide" and in the tutorial referenced above.

AR# 17055
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article