Why do the LUTs in the design appear as black boxes in PrimeTime, and why do they not pass timing?
In the Verilog netlist, functionality of LUT elements is specified with "INIT" strings using the Verilog "defparam" construct. Since PrimeTime accepts only synthesizable Verilog, all simulation constructs (including the "defparam") must be commented out in the Verilog netlist. As a result, LUT elements appear as black boxes to PrimeTime.
However, PrimeTime must be able to understand the functionality of the LUT elements for operations such as case analysis, identification of logical false paths, and justification of false paths. Each LUT function can be replaced with a configured MUX function that reflects the original LUT element's function. There are 3 MUX elements that can be used to replace the 3 types of LUT elements that might appear in the Verilog netlist. These 3 MUX elements can be added to the PrimeTime SIMPRIMS library:
- X_LUT2MUX4 - replaces 2-input LUT elements
- X_LUT3MUX8 - replaces 3-input LUT elements
- X_LUT4MUX16 - replaces 4-input LUT elements
When using ISE 4.2i and newer, MAP primarily uses 4-input LUT elements to implement combinatorial functions in the design; therefore, the simulation netlist contains mostly 4-input LUT elements that will be replaced by X_LUT4MUX16 in the PrimeTime netlist. The xilinx2primetime program reads the Verilog simulation netlist and corresponding SDF file specifically for PrimeTime and generates PrimeTime-compatible Verilog and SDF files containing X_LUT4MUX16 elements. This enables PrimeTime to recognize the functionality of the LUT elements in the netlist.
NOTE: The X_LUT4MUX16 element does not exist in the silicon since it represents the LUT functionality to PrimeTime.
To enable the case analysis, xilin2primetime replaces 4-1 LUT cells in the PrimeTime netlist with configured X_LUT4MUX16 elements to communicate the functionality of the LUT elements to PrimeTime. In the current version of PrimeTime, case analysis might not work properly for 2-1 MUX functions that are described by configured X_LUT4MUX16 elements. PrimeTime may propagate both data pins of the 2-1 MUX to its output when either the "A" side or the "'B" side is selected.
You can work around this problem by using a Tcl function called xp_check, which was codeveloped with Synopsys and is embedded in the ".synopsys_pt.setup" file provided by Xilinx. The xp_check function scans the netlist in PrimeTime, identifies all X_LUT4MUX16 elements that are configured to represent 2-1 MUX, and conditions them for proper propagation of MUX's input to the output during the case analysis. This function is called from PrimeTime's main script after set_case_analysis commands and before issuing report_timing in PrimeTime.
This is a short-term solution. The long-term solution is for PrimeTime to support "defparam" construct in the netlist.