Why do I have to use a free running clock for SysGen Hardware Co-Simulation when using the ADC or DAC?
This is because the ADCs and DACs receive their clock from a XC2V80 chip on the Nallatech BenADDA board, which is used for clock routing. The clock that is going to the ADCs and DACs is a free running clock; therefore, the registers within the User FPGA (XC2V2000 or XC2V3000) that are connected to the ADCs and DACs should be running off the same clock or a glitch could occur.
Because the ADC's and DAC's clock is free running, and not controlled by SysGen, there is no synchronization between the ADCs and DACs and the User FPGA design created in SysGen; thus, during Hardware Co-Simulation the clock must be set to free running.
Please see (Xilinx Answer 18281) for more information about using the clocking of the XtremeDSP Development Kit when doing Hardware Co-Sim.