The Design Guide for the RapidIO Logical Layer interface lists the width of port MGT_A (Management Register Address) input as 8 bits. On the actual interface, this port is 24 bits.
Only 8 bits are needed to address the configuration space in the Logical Layer. The remaining 16 bits can be tied to ground. The extra bits are there for potential future changes in the addressing. The documentation will be changed to reflect the actual port size.