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AR# 17388

8.1i MAP - The physical representation of a latch (as seen in FPGA Editor) appears to have an inverted Gate signal

Description

When I am examining the implementation of a latch (LD or LD_1) in FPGA Editor, it can appear that the Gate signal has been improperly inverted. This is because the hardware representation seen in FPGA Editor is an LD_1. It is therefore correct for an LD to have an inversion added to the Gate signal and for an LD_1 to have an inversion removed from the Gate signal.

Solution

Simulation can be used to verify that the physical design is logically correct.

AR# 17388
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article