This is typically a visual-only problem that occurs during the creation of the RTL schematic.
To verify that a core has been connected correctly after implementation, use the FPGA Editor.
If you are using ISE design tools 6.2i or earlier, a possible cause of the "missing nets" in the RTL view is related to the "Read Cores" option for XST. When this option is selected ("On"), the core will not be connected in the RTL view. You can resolve this issue by unchecking this option and running synthesis again. After you perform these steps, the core will be connected.
If you are experiencing this problem while using the latest software version, please report any missing or incorrect connections to Xilinx Technical Support and provide a test case if possible.