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AR# 17481

6.1i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13"

Description


The following error occurs in XST:



"FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13."



Xilinx is committed to fixing all XST fatal errors and will analyze any problems that you are experiencing in order to improve future versions of XST. Consequently, even if this Answer Record allows you to work around the fatal error, please open a WebCase with Xilinx Customer Support at:

http://support.xilinx.com/support/clearexpress/websupport.htm

Solution


This fatal error is issued for a variety of reasons. Read the last several items in the synthesis report to see what XST was performing last; if this corresponds to one of the synthesis options, turn that option Off and re-run synthesis. XST might bypass the portion in the synthesis engine that is causing the error. First, be sure that the Advanced Options are turned On in ISE:



1. Select the "Edit" pull-down menu in Project Navigator.

2. Select "Preferences."

3. Select the "Processes" tab.

4. Change the Property Display Level from "Standard" to "Advanced."

5. Click "OK."



To select the synthesis options:

1. Highlight the HDL file that you want to synthesize.

2. Right-click the "Synthesize - XST" process.

3. Select "Properties."



The window that appears contains all synthesis properties that are available from the GUI.



NOTE: The most common switch that seems to resolve some fatal errors is the "shift Register Extraction" in the "HDL Options" tab.



XST might generate the fatal error when you infer block RAM/ROM.



This problem has been fixed in the latest 6.1i Service Pack, available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.1i Service Pack 2.



The only other way to work around this problem is to change the RAM/ROM inference from "Auto" to "Distributed" as follows:



1. Highlight the top-level HDL file.

2. Right-click the "Synthesize - XST" process.

3. Select "Properties."

4. Select the "HDL Options" tab.

5. Change the RAM Style (or ROM Style) from "Auto" to "Distributed."

6. Select "OK."



XST generates a fatal error when an array of constants is accessed with dynamic indices:



constant my_2d_array : 2d_array := (000, 111);

T <= my_2d_array(I)(J); -- I and J are signals, not constants



This problem has been fixed in the latest 6.1i Service Pack, available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.1i Service Pack 2.



You can also work around this issue by using an intermediate signal:



constant C : 2d_array := (000, 111);

T1 <= C(I);

T2 <= T1(J);



The above fatal error is produced when ports of Boolean type are used in VHDL:



entity tim_e is

port ( CLK: in std_logic;

d: in boolean;

end tim_e;



architecture behavioral_tim_e of tim_e is



begin

process(CLK)

begin

if (CLK'event) and (CLK = '0') then



if (d = FALSE) then

end if;

end if; --CLK

end process; --CLK

end behavioral_tim_e;





To work around this problem, use different types for the ports:



entity tim_e is

port ( CLK: in std_logic;

d: in std_logic;

end tim_e;



architecture behavioral_tim_e of tim_e is



begin

process(CLK)

begin

if (CLK'event) and (CLK = '0') then



if (d = '1') then

end if;

end if; --CLK

end process; --CLK

end behavioral_tim_e;



In certain circumstances, in mixed language mode, XST issues the fatal error if instantiations do not use all of the ports that are greater than one bit wide:



entity mid_entity;

:

:

u1 : bottom_inst

port map

:

port_bottom (1 downto 0) => port_mid (1 downto 0), -- here port is connected

:

:



module top (...);

:

:

mid_entity u1 (

:

.mid_port[1:0] (), //eventually the port is not connected causing the fatal error

:

:





To work around this problem, connect the unused port to "open" instead of an actual port:



u1 : bottom_inst

port map

:

port_bottom (1 downto 0) => open, -- here port is connected to 'open'

:

:



XST generates the internal error if a declared signal is not "wide" enough for an operation:



reg [11:0] tpkt_size;

:

:



Code says :

tpkt_size [15:8] <= SR_DATA ;



Fixing the signal width resolves the problem.



XST produces a fatal error when a vector that is used in a comparison is also used in a subtraction. When resource sharing is disabled, synthesis of this module results in a fatal error.



If the subtraction of the two registers is pulled out and evaluated in a separate statement, using the resulting delta in the original subtraction statement allows synthesis to complete successfully.



Synthesis of this module produces the fatal error:



Verilog sample code

module test(clk, A, C);

input clk;

input [1:0] A;

input C;



reg [1:0] B;

reg [1:0] D;



always@(posedge clk)

begin

B <= D;

end



// wire delta = B - A;

always@(A or B or C)

begin

if ((B == 2'b00) || (C == 1'b0))

D <= 2'b00 - (B - A);

// D <= 2'b00 - delta;

end



endmodule



If the subtraction is pulled out and evaluated separately, synthesis is successful.



Verilog sample code

module test(clk, A, C);

input clk;

input [1:0] A;

input C;



reg [1:0] B;

reg [1:0] D;



always@(posedge clk)

begin

B <= D;

end



wire delta = B - A;

always@(A or B or C)

begin

if ((B == 2'b00) || (C == 1'b0))

// D <= 2'b00 - (B - A);

D <= 2'b00 - delta;

end



XST issues the fatal error if you have signals declared in a package that you are using.



The only way to work around this problem is to not use the declared signals globally, but to declare the signals in the architectures where they are used.



This error occurs when the install directory for the Xilinx tools contains spaces as in the following:



C:\Program Files\Xilinx



To fix this problem, change the directory to the following:



C:\Xilinx



The fatal error will occur on a construct similar to the following, if resource sharing is turned off:



q <= -(a-b);



To work around this issue, run on resource sharing:



1. Right-click on the synthesize process.

2. Select "Properties..."

3. Select the "HDL Options" tab.

4. Select "Resource Sharing."



Also, this problem has been fixed in the latest 7.1i Service Pack available at:

http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 7.1i Service Pack 1.



This can also occur on signals if they have multiple drivers.
AR# 17481
Date Created 09/03/2007
Last Updated 05/09/2012
Status Archive
Type General Article