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AR# 17491

6.1i ISE - Synthesizing a schematic design gives: "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition..."


Keywords: XST, ECS, Project Navigator, Verilog, VHDL, simulation language, portability, schematic

Urgency: Standard

General Description:
When switching the simulation language from Verilog to VHDL after the Verilog synthesis is run, the following error occurs during the next synthesis run:

"FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a WebCase by clicking on the "WebCase" link at http://support.xilinx.com
ERROR: XST failed
Process "Synthesize" did not complete."


When switching the synthesis/simulation flow, Project Navigator does not delete the XST directory in the Project Directory created by XST. To solve this problem, run Project -> Cleanup Project Files. The Cleanup Project Files process correctly deletes the XST directory. For more information, see (Xilinx Answer 17481).
AR# 17491
Date 02/07/2006
Status Archive
Type General Article
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