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AR# 17501

11.1 Timing Analyzer - Cross-probing does not work consistently with FPGA Editor


Cross-probing does not work consistently on my computer while using ISE. How can I make cross-probing work?


When a logical resource is selected in Timing Analyzer, FPGA Editor occasionally generates the following warning:  


"Unable to select sym LVDS_DATA/SERDES_TX/tx3/ddr_reg3/FF1." 


This is a known problem in correlating logical and physical elements.

AR# 17501
Date 05/20/2014
Status Archive
Type General Article
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