We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17502

6.1i CPLDFit - VHDL/Verilog equations appear to be incorrect


General Description: 

My equations for active low 3-state outputs are incorrect in VHDL and Verilog formats; the enable signal is inverted. 




Given the following logic: 

dout <= din when (en='0') else 'Z' 


The resulting equation is: 

dout <= din when (en='1') else 'Z'


This is only a reporting bug that can be safely ignored; the proper logic is being implemented correctly in the device.

AR# 17502
Date 05/08/2014
Status Archive
Type General Article