My equations for active low 3-state outputs are incorrect in VHDL and Verilog formats; the enable signal is inverted.
Given the following logic:
dout <= din when (en='0') else 'Z'
The resulting equation is:
dout <= din when (en='1') else 'Z'
This is only a reporting bug that can be safely ignored; the proper logic is being implemented correctly in the device.