We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17525

7.1i CPLD - "ERROR:Cpld:1064 - Design rules checking error. Fitting process stopped"


General Description:

When I implement a CPLD design, an error message similar to the following occurs:

"ERROR:Cpld:1064 - Design rules checking error. Fitting process stopped."


This generic error message indicates that the CPLD Fitter did not begin to fit the design because of a violation of the hardware limitations. This error is preceded by another message indicating the cause of the fitting failure, such as too many I/O pins, too many macrocells, or an illegal I/O standard. Check the ISE console window for the error to determine the next course of action.

AR# 17525
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked