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AR# 17527

6.1i XST - "Warning: The following connections close logic loops, and some paths through these connections may not be analyzed"


Keywords: TRCE, Trace, timing, analyzer, XST, retime, retiming

Urgency: Standard

General Description:
After running my design through the implementation tools, Timing Analyzer reports that closed logic loops exist. Why would XST create closed logic loops when my original design did not contain them?


This problem is associated with the re-timing switch. By default, the re-timing switch is off, so if you did not turn it on, closed logic loops probably exist in your design. If you turn the re-timing switch on, XST may erroneously create closed logic loops. The only current way to work around this issue is to keep the re-timing switch off.

This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 17527
Date 03/05/2006
Status Archive
Type General Article
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