UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17553

7.1i CPLD CoolRunner XPLA3 - "ERROR:Cpld:1060 - Design contains X unique output enables, exceeds device limit 9"

Description

General Description: 

When I try to fit a CoolRunner XPLA3 device, the following error occurs: 

 

"ERROR:Cpld:1060 - Design contains X unique output enables, exceeds device limit 9." 

 

How do I know the limit of output enables (OE) for the device?

Solution

For CoolRunner XPLA3, see the "CoolRunner XPLA3 CPLD Family" data sheet, Figure 6: "I/O Cell" located at: 

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-18711&iLanguageID=1
 

Each function block has four Control Terms (CT 3:0) plus one Universal OE. Universal OE is global, so there is one per device. Then you can count the number of output enables available as follows: 

 

1 Universal OE + (# FB x 4) = Total Output Enable limit 

 

This yields the total number of output enables. Note that control terms are shared with other functions, so using a control term clock, control term asynchronous reset or preset, or clock enable reduces the number of output enables that may be used in your design.

AR# 17553
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article