We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 17559

LogiCORE 10 Gigabit Ethernet MAC v3.0 - TX_ACK is asserted for 2 cycles; data is corrupted when minimum IFGs are combined with maximum length frames


Keywords: CORE Generator, COREGen, FIP3, FIP_3, Gigabit, Ethernet, 10, Ten, TX_ACK, IFG, inter-frame gap, corrupt, transmit

Urgency: Standard

General Description:
Due to a problem in the 10 Gigabit Ethernet MAC v3.0 core, maximum length frames can be combined with minimum length inter-frame gaps. Specifically, this causes TX_ACK to pulse for 2 cycles rather than 1 cycle every other time. Additionally, 2 XGMII columns of data are missing, which results in a corrupted frame.


To resolve this issue, apply the following patch to the 5.2i IP Update #3 installation:

Install the patch as follows:
1. Unzip the contents of the zip file or tar.gz archive to the root directory of the Xilinx installation. Select the option to allow the extractor to overwrite all existing files and maintain the directory structure that is pre-defined in the archive.

Determine the Xilinx installation directory by typing the following at the command prompt:
"echo %XILINX%"

Determine the Xilinx installation directory by typing the following:
"echo $XILINX"

NOTE: You may need to have system administrator privileges to install the patch.
AR# 17559
Date 08/31/2006
Status Archive
Type General Article