AR# 17575

|

6.1i XST - XST is not inserting a BUFG on instantiated FDDRRSE primitives

Description

Keywords: dual, data, rate, register, flip-flop, flip, flop, FDDRRSE

Urgency: Standard

General Description:
When I instantiate an FDDRRSE primitive, XST does not put any BUFGs on the clock ports.

Solution

1

This problem is a known issue and will be addressed in a future release. The work-around is to either insert a BUFFER_TYPE constraint into the design or instantiate a BUFGP primitive on the clock port:

Verilog

//BUFFER_TYPE constraint used
module top(d0,d1,ce,c0,c1,rst,q);

input d0,d1,ce,c0,c1,rst;
output q;

FDDRRSE u1 (.D0(d0), .D1(d1), .CE(ce), .C0(c0), .C1(c1), .R(rst), .Q(q));
//synthesis attribute BUFFER_TYPE c0 BUFGP
//synthesis attribute BUFFER_TYPE c1 BUFGP

endmodule

//BUFGP primitive instantiated
module top(d0,d1,ce,c0,c1,rst,q);

input d0,d1,ce,c0,c1,rst;
output q;

wire c0_int, c1_int;

FDDRRSE u1 (.D0(d0), .D1(d1), .CE(ce), .C0(c0_int), .C1(c1_int), .R(rst), .Q(q));
BUFGP u2(.I(c0), .O(c0_int));
BUFGP u3(.I(c1), .O(c1_int));

endmodule

2

This problem is a known issue and will be addressed in a future release. The work-around is to either insert a BUFFER_TYPE constraint into the design or instantiate a BUFGP primitive on the clock port:

VHDL

--BUFFER_TYPE constraint used
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
port(d0, d1, c0, c1, ce, r : in std_logic;
q : out std_logic);
end top;

architecture top_arch of top is

attribute buffer_type : string;
attribute buffer_type of c0 : signal is "BUFGP";
attribute buffer_type of c1 : signal is "BUFGP";

component FDDRRSE is
port (d0 : in std_logic;
d1 : in std_logic;
c0 : in std_logic;
c1 : in std_logic;
ce : in std_logic;
r : in std_logic;
q : out std_logic);
end component;

begin

u1 : FDDRRSE port map
(d0 => d0,
d1 => d1,
c0 => c0_int,
c1 => c1_int,
ce => ce,
r => r,
q => q);

end top_arch;


--BUFGP primitive used
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
port(d0, d1, c0, c1, ce, r : in std_logic;
q : out std_logic);
end top;

architecture top_arch of top is

component FDDRRSE is
port (d0 : in std_logic;
d1 : in std_logic;
c0 : in std_logic;
c1 : in std_logic;
ce : in std_logic;
r : in std_logic;
q : out std_logic);
end component;

component BUFGP is
port (I : in std_logic;
O : out std_logic);
end component;

signal c0_int, c1_int : std_logic;

begin

u1 : FDDRRSE port map
(d0 => d0,
d1 => d1,
c0 => c0,
c1 => c1,
ce => ce,
r => r,
q => q);

u2 : BUFGP port map
(I => c0,
O => c0_int);

u3 : BUFGP port map
(I => c1,
O => c1_int);

end top_arch;
AR# 17575
Date 10/20/2005
Status Archive
Type General Article
People Also Viewed