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AR# 17681

6.1 EDK - How do I use Import Peripheral Wizard in XPS?

Description


Urgency: Standard



General Description:

How do I use the Import Peripheral Wizard in XPS?

Solution


6.1 XPS offers a new tool to allow you to import a user peripheral into XPS, given HDL source files or synthesis projects. Import Peripheral Wizard can be found under the "Tools" tab in the main XPS toolbar menu. The tool is broken up into 12 steps, and the following guides you through the proper selections:



Step 1: Core Name and Version

Enter the name of the peripheral. This name *must* be the name of the top level VHDL entity or Verilog module. For example, if the top-level ".VHDL" entity is named "opb_mycore", then in the Name field, you should enter "opb_mycore".



Clicking on "Use Version Name" is an option and is not required. It provided for you to keep track of core versions. This will append the version to the core name and thus alter the library name of the core. [NOTE: the ".PAO" file that will be created later will reference this library name.]



Step 2: Source File Types

You have an option of HDL source files (.vhd, .v), netlist files (.edn, .edf, .ngo, .ngc), and documentation files (.doc, .txt, .pdf). Selecting "Documentation Files" is optional. If selecting "Netlist Files" option, the top level HDL source file must still be included, so both options must be selected. If just inputting HDL source files, then just select the "HDL Source Files" option.



[NOTE: The HDL source file is expected to already conform to the CoreConnect Bus conventions. Please review the User Core Templates Reference Guide found in the "/doc" directory with the install.]



Step 3: HDL Source Files or Documentation Files

HDL Source Files

You must first select the HDL language used to implement the peripheral. Both VHDL and Verilog are supported. There are three different ways to tell the tool where the files are located. The preferred way is to give either an XST or Synplify project file, as the file will already have passed synthesis, and will contain all appropriate HDL files as well as any libraries. The other option is to browse to your HDL source files. The option "Use existing Peripheral Analysis Order" should only be used if this is the second time around using this tool, and you have made changed to actual HDL code, libraries, or wish to make changes in the upcoming steps.



Documentation

You can import either ".txt", ".doc", or ".pdf" files. This will be stored in the "/doc" folder.



Step 4: HDL Analysis Information

In this step you will need to select your HDL source files as well as any libraries they may use. You are responsible for placing them in the appropriate order that they need to be analyzed. Not providing all libraries or not placing them in the correct order will result in an error. When selecting a library, the tool is expecting the library location and not actual HDL files. Typically libraries that come with the EDK installation are located in the following directory: "%EDK%\hw\LogiCoreLib\pcores\", where "%EDK%" is the location of your root EDK install. For example, if using the "Common_v1_00_a" library, then you should browse to "%EDK%\hw\LogiCoreLib\pcores\Common_v1_00_a". The tool currently will include all files in that library. You can either keep them all in there or remove the unnecessary files.



Step 5: Bus Interfaces

You must select the appropriate bus interface that your core will be attaching to. You have the following options:



Processor Local Bus Interface

- PLB Master and Slave

- PLB Slave



Device Control Register Bus Interface (DCR)

- DCR Slave



On-Chip Peripheral Bus Interface

- OPB Master and Slave

- OPB Slave



Local Memory Bus Interface

- LMB Slave



Step 6: Bus Interface Ports

This step defines the bus interface ports from your peripheral to the bus. The software will parse your HDL source file and try to match up what it can. Whatever remains will need to be manually selected from a pull-down menu.



Step 7: Bus Parameter

Each bus interface has a predefined set of ports and parameters. Typically all you will need to select is the amount of space the peripheral will take up on the bus. The default size is 256 Bytes.



Step 8: Identify Interrupt Signals

If any interrupts exist on the peripheral, you will need to select the appropriate signal(s) and choose whether it is edge- or level-sensitive, and its priority level. If the peripheral has no interrupt, then check "No Interrupt".



Step 9-10: Parameter Attributes

If there are any parameters associated with the peripheral, you can set its default values here. This information will be stored in the ".MPD" file. If you do not wish to do it here, you can always set it in the "Add/Edit Cores" dialog box, or manually enter it into the MHS file. The ".MHS" file always overrides information found in the ".MPD" file.



Step 10: Port Attributes

If you have any ports that require special handling, you can also set their attributes here. This information will be stored in the ".MPD" file. If you do not wish to do it here, you can also set this in the "Add/Edit Cores" dialog box, or manually enter it into the MHS file. The ".MHS" file always overrides information found in the ".MPD" file.



Step 11: Netlist Files

If "Netlist Files" was selected in Step 2, then you will need to browse to the location of these netlist files.



Step 12: Documentation Files

If "Documentation Files" was selected in Step 2, then you will need to browse to the location of the documentation files.





These steps will complete the importing of your new IP into XPS. You will need to exit out of XPS and re-launch in order for the new core to be recognized. The files that Import Peripheral Wizard creates will fall into the following directory structure:



/pcores

/data

/doc

/hdl

/netlist
AR# 17681
Date Created 09/03/2007
Last Updated 06/16/2011
Status Archive
Type General Article